Memory devices that employ an open bit-line architecture can make use of smaller memory cell sizes when compared to that of folded bit-line architectures. In some current examples, an open bit-line architecture may use a 6F2-cell, whereas a 8F2-cell is typically used in a folded bit-line architecture. Drawbacks of the open bit-line architecture include large area penalties in the edge sections, which sections have half of the bit-lines tied to reference voltage (˜Vary/2) as a dummy area for sensing noise immunity. Also, bit-line lengths generally tend to be extended to lengths such as 832-bit or 1K-bit because die size reduction is desirable with improvements in area efficiency and Cd/Cs ratios. However, extended bit-line may have enlarged edge sections, which limits die size reduction because of the accompanying dummy area increase. Operational voltage tends to become lower while, at the same time, process evolution has developed decreased bit-line capacitance and smaller Cd/Cs ratio. In open bit-line scheme, an extended bit-line is not always compatible with smaller die sizes. Typically, there is an optimal bit line length for a given die size. Additionally, under nanofabrication, a memory device's operational voltage tends to be lower due to consideration of transistor reliability. In some instances, sense amplifier imbalances tend not to be improved due to somewhat increased process variation.